Remote, Worldwide 2d ago Not disclosed
RISC-V Linux Jobs
RISC-V is an open-standard instruction set architecture enabling royalty-free processor design. It is disrupting the embedded and IoT silicon market and is gaining traction in data centre accelerators and microcontrollers. Linux support for RISC-V is production-ready, and RISC-V expertise is increasingly sought in semiconductor companies, embedded systems firms, and open hardware organisations.
Boston, Massachusetts, United States May 21 Not disclosed
Redwood City, California, United States May 21 Not disclosed
Santa Clara, California, United States May 21 Not disclosed
San Francisco, California, United States May 21 Not disclosed
San Francisco, California, United States May 21 Not disclosed
BP
Austin, Texas, United States May 21 Not disclosed
Remote, United Kingdom May 20 Not disclosed
Frequently Asked Questions
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RISC-V is an open-standard instruction set architecture (ISA) developed at UC Berkeley and now governed by RISC-V International. Unlike ARM or x86, RISC-V is royalty-free and can be freely implemented by anyone. This enables custom silicon without licensing costs, making it attractive for semiconductor startups, research institutions, and companies wanting architectural freedom.
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Linux has supported RISC-V (riscv64) since kernel 4.15. Major distributions including Fedora, Ubuntu, Debian, and openSUSE provide RISC-V ports. The toolchain (GCC, Clang, LLVM) is mature. Gaps remain in some hypervisor support and enterprise distribution coverage, but RISC-V Linux is production-ready for embedded targets and is improving rapidly for server workloads.
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RISC-V Linux roles are found at semiconductor companies designing RISC-V processors (SiFive, Esperanto, Ventana, Andes), companies developing RISC-V-based microcontrollers (Espressif ESP32-C3, GigaDevice), academic and research institutions, defence and space contractors wanting open, auditable architectures, and cloud providers exploring custom silicon.
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RISC-V Linux roles require deep embedded Linux knowledge, RISC-V ISA understanding (base ISA, extensions: M, A, F, D, C, V for vector), cross-compilation for riscv64, device tree authoring, Linux kernel porting or driver development, and often knowledge of RISC-V privileged architecture (machine mode, supervisor mode, SBI). QEMU emulation skills are useful for development without hardware.